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W972GG6JB
8. OPERATION MODE
8.1
Command Truth Table
CKE
BA2
A13
COMMAND
Previous
Current
BA1
A12
A10
A9-A0
CS
RAS
CAS
WE
NOTES
Cycle
Cycle
BA0
A11
Bank Activate
H
H
BA
Row Address
L
L
H
H
1,2
Single Bank
Precharge
Precharge All
Banks
Write
Write with
Auto-precharge
Read
Read with
Auto-precharge
H
H
H
H
H
H
H
H
H
H
H
H
BA
X
BA
BA
BA
BA
X
X
Column
Column
Column
Column
L
H
L
H
L
H
X
X
Column
Column
Column
Column
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
1,2
1
1,2,3
1,2,3
1,2,3
1,2,3
(Extended)
Mode Register
H
H
BA
OP Code
L
L
L
L
1,2
Set
No Operation
Device
Deselect
Refresh
Self Refresh
Entry
Self Refresh
Exit
Power Down
Mode Entry
Power Down
Mode Exit
H
H
H
H
L
H
L
X
X
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
L
H
L
H
L
H
L
H
X
L
L
X
H
X
H
X
H
H
X
L
L
X
H
X
H
X
H
H
X
H
H
X
H
X
H
X
H
1
1
1
1,4
1,4,5
1,6
1,6
Notes:
1. All DDR2 SDRAM commands are defined by states of CS , RAS , CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA [2:0] determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL = 4 can not be terminated or interrupted. See Burst Interrupt in section 7.5 for details.
4. V REF must be maintained during Self Refresh operation.
5. Self Refresh Exit is asynchronous.
6. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
refresh requirements outlined in section 7.9.
Publication Release Date: Nov. 29, 2011
- 31 -
Revision A02
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